1. Field of the Invention
The present invention relates generally to the structure and manufacturing process of a FET semiconductor device for ESD protection of electronic circuit devices and more particularly to a structure with a guard ring for low capacitance input ESD protection.
2. Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of electrostatic discharge damage (ESD) with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits which allows the ESD current to be shunted to an alternative voltage source, typically ground, protecting the active internal circuits from damage.
There can be several different types of device structures used for these protective devices, such as single diodes, stacked diodes, field effect transistor (FET) devices, and silicon controlled rectifiers (SCR).
With prior art devices, the capacitance associated with the ESD protection device on the active circuit input pad could be a concern as circuit speeds increase. A typical prior art protection circuit scheme is represented in FIG. 1A. The active circuit input-output (I/O) terminal or pad 10 is connected to the ESD protection circuit devices ESD-1 element 12 with associated parasitic capacitance C12 and parasitic diode D12, and protection device ESD-2 element 14 with associated parasitic capacitance C14 and parasitic diode D14. The I/O pad 10 is also connected to the input or output stage of the active logic circuits A. Also shown in FIG. 1 is the protection devices ESD-Vcc element 16 with associated parasitic capacitance 16 and parasitic diode D16 that protects against high ESD voltages occurring on the circuit power lines Vcc and Vss.
A positive ESD voltage at the input pad 10 would turn on diode D14 and ESD-1 12 providing a suitable discharge path for the ESD energy. For a negative ESD event on the I/O pad 10, diode D 12 is placed into a conducting mode, as is ESD-Vcc 16, again providing a suitable discharge path for the ESD energy.
Typical prior art protection devices are shown in schematic form in FIG. 1B. Protection device ESD-1 is shown as a N channel metal oxide semiconductor (NMOS) 12, and ESD protection device ESD-2 is shown as a P channel MOS (PMOS) 14. The ESD-Vcc protection device is shown as a NMOS device 16. FIG. 1C shows a representative cross-section of the ESD protection circuit devices. NFET 12 has its source 12 S connected to its gate 12G and to the Substrate 20 P+ contact 22 and to a second voltage source Vss, typically ground. The NMOS 12 drain D12 is connected to the ESD-2 PMOS protection device 14 drain 14D. The gate 14G of ESD-2 PMOS protection device 14 is connected to its source element 14S and to the source 16S of ESD-VCC NMOS protection device 16 and subsequently to a first voltage source Vcc.
Although the prior art circuit shown in FIG. 1B provides ESD protection for the active devices, the stray or parasitic capacitance C12 and C13 impose undesired capacitive loading to the I/O pad and logic circuit input stage A.
The invention provides a unique structure and method to eliminate some of this capacitance on the I/O pad while still providing appropriate ESD protection.
The following patents and reports pertain to ESD protection.
U.S. Pat. No. 6,097,066 (Lee et al.) shows an ESD structure with a third ring shape serving as a guard ring.
U.S. Pat. No. 5,714,784 (Ker et al.) reveals an ESD structure with guard rings.
U.S. Pat. No. 5,637,900 (Ker et al.) shows an ESD structure with P+ guard rings.
U.S. Pat. No. 6,249,413 (Duvvury) and U.S. Pat. No. 5,905,287 (Hirata) show related ESD structures and guard rings.